1. Field of the Invention
The present invention is directed generally toward a method and apparatus for protection of data utilizing cyclical redundancy checking (CRC) and more specifically relates to methods and structure for loading CRC values into a CRC value cache memory with minimal overhead.
2. Discussion of Related Art
In a high-performance computer system consisting of multiple processors and mass storage devices, it is of critical importance that all information be stored and retrieved reliably with no errors. It is of equal importance that if errors occur in the storage or retrieval of data, that the errors be detected and reported. Typically, the mass storage of a high-performance computer system consists of a redundant array of independent disks (RAID). Within the RAID mass storage system, data is stored both in semiconductor memory in the RAID controller and on the magnetic media of the RAID disk drives. A storage controller in such a RAID subsystem manages the transfer of information between semiconductor memory associated with the controller and the storage devices (i.e., disk drives). In a RAID subsystem, all data is stored with redundancy information to enhance reliability and to permit continued operation through various failures.
Though data written to semiconductor memory can be protected using error correction code (ECC) techniques, this will not prevent against inadvertent writes to locations in the memory or reading from incorrect locations. Furthermore, data stored on the disk drives of a RAID system can be stored incorrectly or retrieved incorrectly due to errors in the drives. For example, the drives or connections to the drives may have physical problems, data may be stored in the wrong location on the drive, or the data may become corrupted.
The method by which these errors are detected in the system should have minimum impact on the overall system performance. There are several approaches that may be used to protect data from the above-mentioned errors. One method involves the execution of software that checks the integrity of data as it is being stored or retrieved. This method, used to ensure the accuracy of transmitting digital data, is cyclical redundancy checking (CRC). This operation executes concurrently with the transfer of the data. Because this method utilizes a portion of the computing resources for its execution, the overall performance of the system is reduced. This method adds an additional amount of complexity to the software executing in the RAID system.
Another method involves a hardware engine that checks the integrity of data after it has been transferred. Though this method utilizes a small amount of computing resources to initialize and start the hardware engine, system performance is reduced due to the time required to initialize the engine and execute the checking algorithm. If a separate hardware engine is used to perform the CRC function after a transfer to or from system memory is completed, then the next system operation or transfer would have to wait until this CRC operation is completed before executing. This reduces system performance.
The parent patent application provides the addition of a dedicated hardware CRC computation engine integrated with the memory controller of the storage controller to assure the integrity of data transferred between the system memory and storage devices. The CRC computation engine provides CRC calculation xe2x80x9con-the-flyxe2x80x9d for the protection of data transferred to and from the system memory without software overhead. The computation of CRC values and optional checking against previously calculated CRC values is selected through the use of an address-mapping scheme. The CRC protection scheme of the parent application requires a small amount of initial software overhead to allocate the data, CRC value, and CRC error regions of the system memory. After the CRC protection scheme is initialized, all CRC operations are transparent to the executing software.
The parent application further provides a separate cache memory for storing recently utilized CRC values. In the parent application, an exemplary preferred embodiment discloses multiple devices coupled through the memory interface each capable of generating transactions involving CRC values. A CRC engine generates CRC values as host supplied data is initially transferred to system memory of the storage controller. The generated CRC values are stored in system memory for later use. The parent application points to use of a cache for CRC values to expedite accesses to CRC values when used subsequently to check data transferred between the storage devices and the storage controller""s system memory. Where all such CRC values are cached together, it remains a problem to rapidly locate a particular cached CRC value entry. Searching through a single hierarchy of the CRC value cache can negatively impact overall system performance. The sibling patent application presents methods and structure for improving system performance by reducing overhead in processing CRC values in CRC value cache memory. As other CRC values are generated, older values in cache may be replaced. It is often the case that later data exchanges to/from the storage devices and from/to the system buffer memory will have to re-read stored CRC values that are not present in the CRC cache memory.
It remains a problem that loading of CRC values into the CRC value cache memory for checking of blocks exchanged between system memory and the storage devices requires two accesses to the system memory. A first access moves the CRC values to or from system memory when the associated data block is accessed on the disk drives and a second access moves the CRC values from system memory to the CRC value cache memory when the associated data block is accessed in system memory. The extra memory access to load CRC values in CRC value cache memory negatively impacts overall system performance by adding extra arbitration overhead for access to system memory and by adding additional read cycles on the system memory to re-read the stored CRC values.
It is evident from the above discussion that a need exists for an improved method and structure for loading CRC values into a CRC value cache memory from system memory.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing structure and methods for reducing overhead processing when loading CRC values from system memory into a CRC value cache memory. More specifically the invention provides that CRC values are loaded into CRC cache memory in parallel with system memory access of CRC values relating to access to the storage devices. In other words, when CRC values are transferred to/from system memory from/to the disk drives of the storage system, structure and methods of the invention detect the transfers and load the CRC values into CRC value cache memory in parallel with the detected transfers. This mode of the present invention used to load CRC values into CRC cache memory is also referred to herein as xe2x80x9cfly-byxe2x80x9d mode. This fly-by feature of the invention reduces overhead processing associated with a need for a second access to system memory to load CRC values into CRC value cache memory.
Still more specifically, circuits of the present invention monitor the memory accesses by the processor of the storage controller to system memory in the controller. When CRC values are transferred from/to system memory in conjunction with associated disk drive transfers, the CRC values are captured by the CRC engine and stored in CRC value cache memory substantially in parallel with the transfers from/to system memory. These structures and methods of operation obviate the need for a second access to system memory specifically to load CRC values from system memory to the CRC value cache memory.
A first feature of the invention therefore provides a method in a system having a plurality of disk drives coupled to a storage controller having system memory and a CRC value cache memory, a method for loading CRC values into the cache memory comprising the steps of: monitoring access to the system memory by the storage controller; detecting normal mode accesses by the storage controller to CRC values in the system memory such that the normal mode accesses exchange the CRC values between the system memory and storage devices coupled to the storage controller; and loading the CRC values into the cache memory substantially in parallel with the detected normal mode access.
Another aspect of the invention further provides that the step of detecting includes the step of: determining that an address associated with the access is within a range of normal mode access addresses to determine that the access is a normal mode access.
Another aspect of the invention further provides that the step of determining comprises the step of: comparing the address against normal mode base and limit registers to determine that the access is within the range of normal mode access addresses.
Another aspect of the invention further provides that the step of determining comprises the steps of: comparing the address against generate mode base and limit registers to determine that the access is not within a range of generate mode access addresses; and comparing the address against check mode base and limit registers to determine that the access is not within a range of check mode access addresses.
Another aspect of the invention further provides that the step of detecting further includes the step of: determining that the address is within a range of CRC value access addresses to determine that the access is a normal mode access to CRC values in the system memory.
Another aspect of the invention further provides that the step of determining that the address is within a range of CRC value access addresses comprises the step of: comparing the address against CRC value base and limit registers to determine that the access is accessing CRC values in the system memory.
Another feature of the invention provides in a system having a plurality of disk drives coupled to a storage controller having system memory and a CRC value cache memory, an apparatus for loading CRC values into the cache memory comprising: means for monitoring access to the system memory by the storage controller; means for detecting normal mode accesses by the storage controller to CRC values in the system memory such that the normal mode accesses exchange the CRC values between the system memory and storage devices coupled to the storage controller; and means for loading the CRC values into the cache memory substantially in parallel with the detected normal mode access.
Another aspect of the invention further provides that the means for detecting includes: means for determining that an address associated with the access is within a range of normal mode access addresses to determine that the access is a normal mode access.
Another aspect of the invention further provides that the means for determining comprises: normal mode base and limit registers for defining the range; and means for comparing the address against the normal mode base and limit registers to determine that the access is within the range of normal mode access addresses.
Another aspect of the invention further provides the means for determining comprises: generate mode base and limit registers for defining a generate mode range of access addresses; check mode base and limit registers for defining a check mode range of access addresses; means for comparing the address against the generate mode base and limit registers to determine that the access is not within the generate mode range of access addresses; and comparing the address against the check mode base and limit registers to determine that the access is not within the check mode range of access addresses.
Another aspect of the invention further provides that the means for detecting further includes: means for determining that the address is within a range of CRC value access addresses to determine that the access is a normal mode access to CRC values in the system memory.
Another aspect of the invention further provides that the means for determining that the address is within a range of CRC value access addresses comprises: CRC value base and limit registers for defining a range of CRC value access addresses; and means for comparing the address against the CRC value base and limit registers to determine that the access is accessing CRC values in the system memory.
Another feature of the invention provides for a storage subsystem comprising: a plurality of storage devices for storing data blocks and CRC values corresponding to the data blocks; and a storage controller coupled to the plurality of storage devices for controlling operation of the storage subsystem such that the storage controller includes: system memory for storing the CRC values such that the storage controller exchanges the CRC values between the system memory and the plurality of storage devices using a normal mode memory transaction; a CRC value cache memory for storing the CRC values; and a fly-by transfer element coupled to the system memory and coupled to the CRC value cache memory for loading the CRC values into the CRC value cache memory substantially in parallel with the normal mode memory transaction.
Another aspect of the invention further provides that the storage controller further includes: a memory controller coupled to the system memory and providing an interface for other components of the storage controller to access the system memory, such that the fly-by transfer element is coupled to the system memory through the memory controller.
Another aspect of the invention further provides that the memory controller includes: a memory monitor bus adapted to enable the fly-by transfer element to detect the normal mode memory transaction.
Another aspect of the invention further provides that the memory controller further includes: a normal mode detector coupled to the memory monitor bus to detect the normal mode memory transaction and to apply a signal to the memory monitor bus indicating detection of the normal mode memory transaction.
Another aspect of the invention further provides that the normal mode detector comprises: normal mode base and limit registers for defining a range of normal mode access addresses; and a comparator for comparing an access address on the memory monitor bus against the normal mode base and limit registers to determine that the memory access is within the range of normal mode access addresses.
Another aspect of the invention further provides that the normal mode detector comprises: generate mode base and limit registers for defining a generate mode range of access addresses; check mode base and limit registers for defining a check mode range of access addresses; a comparator for comparing an access address on the memory monitor bus against the generate mode base and limit registers to determine that the access is not within the generate mode range of access addresses and for comparing the address against the check mode base and limit registers to determine that the access is not within the check mode range of access addresses.